Referring to FIG. 1, a photolithography system 100 is used for patterning integrated circuit structures on a semiconductor wafer 102. In the photolithography system 100, a reticle 104 has a pattern of polygons thereon to be patterned onto the semiconductor wafer 102. Light from a light source 106 is illuminated through the pattern of polygons on the reticle 104 onto the semiconductor wafer 102. In addition, a lens system 108 is used within the photolithography system 100 to typically reduce the image of the pattern of polygons on the reticle 104 onto the semiconductor wafer 102. The pattern of polygons on the reticle 104 are typically opaque to the light from the light source 106.
A photoresist material on the semiconductor wafer 102 is cured when light from the light source 106 reaches the photoresist material and is not cured otherwise. When the photoresist material is then developed, cured photoresist material may be etched away while the uncured photoresist material remains, and the remaining uncured photoresist material may further act as a mask for etching away exposed material deposited below the photoresist material. Thus, when the light from the light source 106 does not reach the semiconductor wafer 102 for the pattern of opaque polygons on the reticle 104, the pattern of polygons on the reticle 104 is transferred to the photoresist material on the semiconductor wafer 102. Such a photolithography system 100 is known to one of ordinary skill in the art of integrated circuit fabrication.
A long-recognized important objective in the constant advancement of IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
As the dimensions of integrated circuit structures are constantly scaled down such that a desired dimension of an integrated circuit structure is smaller than the wavelength of the light from the light source 106 within the photolithography system 100, the shape and dimensions of the structure formed on the semiconductor wafer 102 is distorted from non-linear light diffraction and optical proximity effects, as known to one of ordinary skill in the art of photolithography. Thus, the wavelength of light from the light source 106 is desired to be lowered to 193 nm (nanometer), 157 nm (nanometer), or EUV (extreme ultraviolet) light technology from 248 nm (nanometer) technology.
Referring to FIG. 2, a layer of dielectric material 112 formed on a semiconductor substrate 114 is desired to be patterned with an opening formed through the layer of dielectric material 112. For example, the opening formed through the layer of dielectric material 112 may be a trench or a via hole to be subsequently filled with a conductive material such as copper for forming a metal line or a via structure for interconnect of an integrated circuit. In that case, the layer of dielectric material 112 is comprised of a low-K dielectric material having a dielectric constant that is lower than the dielectric constant of silicon dioxide (SiO2). Such a low-K dielectric material surrounding interconnect structures is advantageous for lower capacitance between the interconnect structures. Such lower capacitance results in higher speed performance of the integrated circuit and also in lower power dissipation. In addition, such lower capacitance results in lower cross-talk between the interconnect structures. Lower cross-talk between interconnect structures is especially advantageous when the interconnect structures are disposed closer together as device density continually increases.
An example of the low-K dielectric material forming the layer of dielectric material 112 referred to by the name of “Black-Diamond”™ is commercially available from Applied Materials, Inc., headquartered in Sunnyvale, Calif. Such a low-K dielectric material is comprised of the elements silicon, carbon, oxygen, and hydrogen.
Referring back to FIG. 2, the layer of dielectric material 112 is deposited onto a layer of etch-stop material 116 which is in turn deposited on a layer of underlying material 118. For example, when the opening to be patterned through the layer of dielectric material 112 is a via hole, the underlying material 118 is comprised of metal of an underlying metal line structure. Alternatively, when the opening to be patterned through the layer of dielectric material 112 is a trench, the underlying material 118 is comprised of a dielectric material. The layer of etch-stop material 116 is comprised of silicon nitride (Si3N4) or silicon carbide (SiC).
In addition, a layer of capping material 120 is deposited on the layer of dielectric material 112. The layer of capping material 120 is comprised of silicon dioxide (SiO2). Then, a layer of photoresist material 122 is deposited on the layer of capping material 120. For patterning integrated circuit structures with reduced dimensions, the photoresist material 122 is for a photolithography system using the lower wavelength of 193 nm (nanometer), 157 nm (nanometer), or EUV (extreme ultraviolet) rather than 248 nm (nanometer). Such photoresist material 122 for a photolithography system using the lower wavelength of 193 nm (nanometer), 157 nm (nanometer), or EUV (extreme ultraviolet) is known to one of ordinary skill in the art of integrated circuit photolithography.
Referring to FIG. 3, for patterning an opening through the layer of dielectric material 112, an opening 124 is patterned through the layer of photoresist material 122 within a photolithography system, such as the photolithography system 100 of FIG. 1. Referring to FIG. 4, the region of the layer of capping material 120 and the layer of dielectric material 112 exposed through the opening 124 of the layer of photoresist material 122 is etched away until the etch-stop material 116 is exposed at the bottom wall of the opening 124. When the layer of dielectric material 112 is comprised of the low-K dielectric material comprised of the elements silicon, carbon, oxygen, and hydrogen, such as the “Black-Diamond”™ dielectric material, an aggressive etch process using fluorine plasma is used to etch the opening through the layer of dielectric material 112. Referring to FIGS. 4 and 5, after etching the opening 124 through the dielectric material 112, the remaining photoresist 122 is removed in a subsequent etch process using oxygen plasma.
Further referring to FIG. 4, however, the photoresist material 122 is also etched away during the etching of the opening 124 through the low-K dielectric material 112 because the etch selectivity (i.e., the ratio of the etch rate of the low-K dielectric material 112 to the etch rate of the photoresist material 122) is not high. In addition, such etch selectivity decreases even further when the photoresist material 122 is for a photolithography system using the lower wavelength of 193 mn (nanometer), 157 nm (nanometer), or EUV (extreme ultraviolet) rather than 248 nm (nanometer). For example, when the photoresist material 122 is for a photolithography system using the lower wavelength of 193 nm (nanometer), 157 nm (nanometer), or EUV (extreme ultraviolet) and when the low-K dielectric material 112 is comprised of the “Black-Diamond”™ dielectric material, the selectivity of the photoresist material 122 to the low-K dielectric material 112 in an etch process using fluorine plasma is 2:1 (i.e., in that case, the low-K dielectric material 112 etches two-times faster than the photoresist material 122).
Further referring to FIG. 4, because of such low etch selectivity between the photoresist material 122 and the low-K dielectric material 112, the photoresist material 122 is also etched away by the fluorine plasma during the etch process for etching the low-K dielectric material 112. When the photoresist material 122 is etched away near the top corners 126 of the opening 124 formed by the low-K dielectric material 112, such top corners 126 are etched away to result in rounding at such corners 126 of the opening 124. Such rounding of the top corners 126 results in profile degradation of the structures to be patterned within the low-K dielectric material 112.
A thicker layer of photoresist material 122 may be used to ensure that the photoresist material 122 is not etched away from the top corners 126 of the opening 124 during the etch process for etching the opening 124 through the dielectric material 112 to prevent such profile degradation. However, the thicker layer of photoresist material 122 may not be developed properly with the light source of the photolithography system through-out the greater depth of the thicker photoresist material 122. The depth of focus for developing the photoresist material 122 by the light source of the photolithography system is limited. Furthermore, the depth of focus for developing the photoresist material 122 decreases when the wavelength of light from the light source of the photolithography system decreases. Thus, when the wavelength of light from the light source of the photolithography system is desired to be lowered to 193 nm (nanometer), 157 nm (nanometer), or EUV (extreme ultraviolet) technology from 248 nm (nanometer) technology, the thickness of the photoresist material 122 should be minimized rather than increased.
Furthermore, increasing the thickness of the photoresist material 122 is further disadvantageous because such thicker photoresist material 122 increases the aspect ratio of the opening formed through such photoresist material 122 and the dielectric material 112. Etching an opening with higher aspect ratio is more difficult as known to one of ordinary skill in the art of integrated circuit fabrication.
Thus, a mechanism is desired for preventing profile degradation during etch of an opening through a dielectric material with a photoresist material having low etch selectivity from the dielectric material without increasing the thickness of the photoresist material.